Using PlanAhead With PR

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Contents 1 Note 2 New Project Wizard 3 Setup PlanAhead Reconfigurable Project 4 Set PBlocks 5 Placing Socket Bridge Macros 6 Place Global Clocks 7 Place HWICAP 8 Placed Components 9 Run DRC 10 Modify ExploreAhead Runs Options 11 Launch Runs (for Static) 12 Launch Runs (For PR Modules) 13 PR Assemble

Note

Even though the PR tools are installed for 9.1i, we are using 10.1i PlanAhead (which is OK).

Make sure you have the "pr_settings.sh" sourced from the hardware base system tutorial.

New Project Wizard

1. Launch PlanAhead: planAhead
2. Create a New Project
3. Name the project (this creates a directory with the same name)

4. Yes, Import a Syntheiszed (EDIF or NGC) netlist

5. Browse to the implementation/system.ngc file
6. Add the following 3 Netlist Directories:
6a. implementation/opb_prr_0_wrapper
6b. implementation/opb_prr_1_wrapper
6c. bus_macros
6c. Copy bus_macros directory to your main project directory from: /build/willk/rtr/linux_nopci_linux/bus_macros

7. Select Virtex4

8. Name Floorplan (Optional, I leave it floorplan_1)

9. Choose Part: xc4vfx60ff1152-11
9a. Virtex4 Chip on the ML410

10. Add system.ucf Constraints file (data\system.ucf)

Setup PlanAhead Reconfigurable Project

NOTE: This is just a SIMPLE example, it is assumed you already have an idea of what hardware modules will go in the PR Regions.

1. Set Project to be a PR Project: File -> Set PR Project
2. Set PR Modules (opb_prr_0 and opb_prr_1) to Reconfigurable: Right Click and Select Set Reconfigurable
   • The user_logic.vhd for the opb_prr hardware core has initial functionality, say simple Read and Write Register capabilities. You want to name the Module something like "reg". This is the "first" PR Module for the PR Region that you will add. You can make changes to the user_logic.vhd, re-generate nestlists and add them as additional PR Modules (named say "add" and "lin").
3. Assuming that you have created 3 Modules ("reg", "add" and "lin"), if not follow these steps:
   • Create a directory called something like "pr_ngcs"
   • Create subdirectories under pr_ngcs as "reg" "add" and "lin"
   • Copy implementation/opb_prr_*_wrapper.ngc into prr_ngcs/reg
   • Modify opb_prr_v1_00_a/hdl/vhdl/user_logic.vhd:
     • Add: Add A process that will store into slv_reg3 <= slv_reg0 + slv_reg1 + slv_reg2
   • Generate Netlist
   • Copy implementation/opb_prr_*_wrapper.ngc into prr_ngcs/add
   • Modify opb_prr_v1_00_a/hdl/vhdl/user_logic.vhd:
     • Lin: Add A process that will store into slv_reg3 <= slv_reg0 * slv_reg1 + slv_reg2
   • Generate Netlist
   • Copy implementation/opb_prr_*_wrapper.ngc into prr_ngcs/lin
4. Right Click on PRR0 -> Add Reconfigurable Module
5. Give a short name "add"
6. Select "add" ngc generated above
7. Repeat for any additional Modules

Set PBlocks

Set PR Block Size (assign PR Region on FPGA):

1. Select the "Create Site Constraint Mode" Button
2. Right Click on pblock_opb_prr_0
3. Select Set PBlock Size
4. Draw PBlock for opb_prr_0
   • Ideal location so far is between PPC0 and PPC1 (leaving 2 columns of CLBs between Region and Center Column
5. Repeat for pblock_opb_prr_1
   • Ideal location so far is on the Right Hand Column (again leaving 2 columns of CLBs between Region and Center Column)

Placing Socket Bridge Macros

1. Expand opb_socket_bridge_left_0
2. Expand Primitives
3. Place the following components in the following order
   • Left Socket Bridge means the Macros will appear on the Left side of the PR Region
   • So Left = opb_prr_1 (or the "right" PR module) it is confusing... initially
4. The order is:
   • Control1_BM
   • [0].ABUS_BM
   • [1].ABUS_BM
   • [2].ABUS_BM
   • [3].ABUS_BM
   • [0].SDBUS_BM
   • [1].SDBUS_BM
   • [2].SDBUS_BM
   • [3].SDBUS_BM
   • Control2_BM
   • [0].DBUS_BM
   • [1].DBUS_BM
   • [2].DBUS_BM
   • [3].DBUS_BM
5. Repeat for Right Socket Bridge (but place them on opb_prr_0) on the Right Side of the Module

Place Global Clocks

Select Edit -> Find all instances of the Global Clocks. Place the clocks (and DCM) on the top half of the chip.

The order doesn't matter for the Global Clocks.

Place the 1 DCM above the other DCM (which is a little above the Global Clocks)

Place HWICAP

There are two HWICAPs that can be placed, place yours at the top one (6th in the column)

Placed Components

Run DRC

Run the Design Rules Check from Tools -> DCR

You will likely get between 110 - 130 errors. If they are yellow or orange it is ok, if it is Red, fix it.

Common problems are putting the Bus Macros on the wrong "side" of the PR Region, or forgetting to place the Clocks, DCM or HWICAP.

Modify ExploreAhead Runs Options

1. Static
   • -bm: implementation/system.bmm
   • -timing: True
   • -ol (under Map): High
   • -ol (under PAR): High
2. All PR Modules (You have do do this for each of them)
   • -timing: True
   • -ol (under Map): High
   • -ol (under PAR): High

Launch Runs (for Static)

Starting with the Static Layout, Right Click and Select Launch Runs This will take a good 15 - 20 minutes

Launch Runs (For PR Modules)

After running the Static Run, Launch the Runs for the PR Modules.

These take much less time (3 - 5 minutes / modules). You can select all of them and select Launch Runs to queue them up so you don't have to sit there and select one after the other.

PR Assemble

In the ExploreAhead Runs tab, Right Click on Static and Select PR Assemble to generate Bitstreams

This will generate bitstreams:

1. static_full.bit
   • Equivalent to system.bit with the checked PR Modules initialized in the PR regions
2. opb_prr_0_add_partial.bit
3. opb_prr_1_add_partial.bit
4. opb_prr_0_reg_partial.bit
5. opb_prr_1_reg_partial.bit
6. opb_prr_0_lin_partial.bit
7. opb_prr_1_lin_partial.bit

These bitstreams are located in the: planahead/planahead.runs/floorplan_1/merge

Next, Follow the Generating Partial Reconfiguration Bitstream for the ML-410 Tutorial