Overview of the interface

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About

• Author: Liu Hu
• Last Modified: 2/19/2009
• Notes1: These tutorials will describe how to connect user IP core to APU (Auxiliary processor unit) via FCB (Fabric co-processor bus) using the FCM interface, and utilize it in software applications. A double precision FPU is used as an sample IP core that is connected to the FCM interface.
• Notes2: If the reader just get started with FPGA/Linux mixed design, it is recommend to refer to Andy's tutorial Linux 2.6 on ML-410 first to learn how to create a base system.

APU Introduction 

The Auxiliary Processor Unit (APU) controller allows the designer to extend the native PowerPC 405 instruction set with custom instructions that are executed by an FPGA Fabric Coprocessor Module (FCM).

The APU controller performs two main functions:

1. It provides a synchronization mechanism between the PowerPC processor and the FCM running at a lower clock rate.

2. It decodes instructions or allows the FCM to decode instructions. Execution, however, is always carried out by the FCM.

This enables a much tighter integration between an application specific function and the processor pipeline than is possible using, for example, a bus peripheral.

Figure 1 shows the pipeline flow between the PowerPC 405 Core, the APU controller, and the Fabric Coprocessor Module.

What is FCB?

In a system with multiple FCMs, it can be helpful to use an interface provided by XPS called the Fabric Coprocessor Bus (FCB). The FCB is a multiplexer that allows the APU to be connected to more than one FCM. Using XPS, an FCB can be readily instantiated and deployed in a system, saving the need to create an APU‐to‐FCM interface from scratch.

Introduction to FCB to FCM interface

As you can see from figure 3, the interface I created is between FCB and userlogic，it provides basic write and read functions, and wait user core state.

Here is the brief specification of the interface:

1. Hardware
   • four 32 bit registers as write registers
     • slv_reg0 slv_reg1 slv_reg2 slv_reg3
   • two 32 bit registers as read registers
     • slv_reg4 slv_reg5
   • fcmuserdata is data signal from this fcm interface to userlogic core 128bit
   • userfcmdata is data signal from userlogic core to fcm interface regs 64bit
2. Software implementation
   • use extension instruction lqfcmx or ldfcmx in your application program to load data into write registers
   • use extension instruction stdfcmx intruction in your application program to store result data back into memory

The following figure shows the main state machine of this fcm interface:

Now you have a basic idea of the FCM interface, let's continue on to the Creating a Hardware Base System with FCB connected to APU and enable APU