Linux on both PPCs

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Follow these steps to create a hardware base system with two PowerPCs, each running Linux. These are two Separate System on one Chip. Future tutorials may cover processor to processor communication.

This assumes you are using Xilinx 10.1i Tools

Contents

Base System Builder Wizard

Run Base System Builder and Select the following Options

Screen 1:

Screen 2 (Select Board):

  • Xilinx
  • Virtex-4 ML410 Evaluation Platform
  • C

Screen 3 (Select Processor):

  • PowerPC

Screen 4 (Configure PowerPC Processor):

  • Processor Clock Frequency to 300.00 MHz

Screen 5 (Configure IO Interfaces 1 of 5): Select Both RS232 UARTs

  • Peripheral: XPS UARTLITE
  • Baudrate: 115200
  • Data bits: 8
  • Parity: None
  • Use Interrupt: Check

Screen 6 (Configure IO Interfaces 2 of 5):

  • SPI_EEPROM: Uncheck
  • LEDs_8BIT: Uncheck
  • LCD_OPTIONAL: Uncheck
  • pci_arbiter_0: Uncheck

Screen 7 (Configure IO Interfaces 3 of 5):

  • PCI32_BRIDGE: Uncheck
  • SysACE CompactFlash: Uncheck [Later you might want to add this back]
  • IIC_Bus: Uncheck [Later you might want to add this back]
  • Ethernet_MAC: Uncheck

Screen 8 (Configure IO Interfaces 4 of 5):

  • TriMode_MAC_MII: Uncheck
  • MGT_Wrapper: Check [ALWAYS CHECK THIS!]
    • MGT Protector is used to drive the MGTs with a signal to preserve their functionality, without it Will's board would not work

Screen 9 (Configure IO Interfaces 5 of 5):

  • DDR2_SDRAM: Check
  • DDR_SDRAM: Check

Screen 10 (Add Internal Peripherals 1 of 1):

  • xps_bram_if_cntlr_1: 64 KB
  • xps_bram_if_cntlr_2: 64 KB
    • Add Peripheral -> XPS BRAM IF CNTLR -> Set to 64 KB Memory Size

Screen 11 (Software Setup):

  • Memory Test: Uncheck
  • Peripheral Test: Uncheck

Screen 12 (System Created)

  • Click Generate

Adding Components to XPS System Assembly View

The System will consist of two PowerPCs, each connected to a BRAM, Main Memory (DDR or DDR2), Interrupt Controller, and a UART. Most of these components have already been added; however, to break the system up into two SoCs you need to add more components. The next section will explain how to connect everything together.


  1. Add Processor -> PowerPC 405 Virtex-4
  2. Add Clock, Reset and Interrupt -> XPS Interrupt Controller
  3. Add Bus and Bridge -> Processor Local Bus (PLB) 4.6
  4. Add Bus and Bridge -> Processor Local Bus (PLB) 4.6
  5. Add Bus and Bridge -> Processor Local Bus (PLB) 4.6

Renaming Components

Now that you have added all of the components, we will rename them make connection easier.

  1. Rename ppc405_virtex4_0 -> ppc405_1
  2. Rename plb -> plb_0
  3. Rename plb_v46_0 -> plb_1
  4. Rename plb_v46_1 -> ppc405_1_dplb
  5. Rename plb_v46_2 -> ppc405_1_iplb
  6. Rename ppc405_0_dplb1 -> ppc405_0_dplb
  7. Rename ppc405_0_iplb1 -> ppc405_0_iplb
  8. Rename xps_bram_if_cntlr_1 -> xps_bram_if_cntlr_0
  9. Rename xps_bram_if_cntlr_2 -> xps_bram_if_cntlr_1
  10. Rename plb_bram_if_cntlr_1_bram -> plb_bram_if_cntlr_0_bram
  11. Rename plb_bram_if_cntlr_2_bram -> plb_bram_if_cntlr_1_bram
  12. Rename RS232_Uart_1 -> RS232_Uart_0
  13. Rename RS232_Uart_2 -> RS232_Uart_1

(renamed_components.jpg)

Connecting Components in XPS System Assembly View

Now that all of the components are named more sensibly, connect each component in the following way. (Any left out of this list should rename connected as it was).

  1. ppc405_1
    • RESETPPC -> proc_sys_reset_0_RESETPPC1
    • JTAGPPC -> jtagppc_cntlr_0_JTAGPPC1
    • IPLB1 -> ppc405_1_iplb
    • DPLB1 -> ppc405_1_dplb
    • IPLB0 -> plb_1
    • DPLB0 -> plb_1
  1. DDR_SDRAM
  • Double Click DDR_SDRAM to bring up configuration window
    • Add PORT1 of type PLBV46

(ddr_sdram.jpg)

  • SPLB1 -> ppc405_1_dplb
  • SPLB0 -> ppc405_1_iplb
  1. xps_bram_if_cntlr_1
  • SPLB -> plb_1
  1. xps_intc_1
  • SPLB -> plb_1
  1. RS232_Uart_1
  • SPLB -> plb_1

(connections.jpg)

Generating Addresses

Click the Addresses Tab and Click "Generate Addresses"

(addresses.jpg)

Software Platform Settings

Software -> Software Platform Settings

For Each Processor Instance:

  1. ppc405_0
  • Software Platform
    • OS: linux_2_6
  • OS and Libraries
    • Connected_Periphs -> RS232_Uart_0 and xps_intc_0
    • Memory Size -> 0x10000000
  1. ppc405_1
  • Software Platform
    • OS: linux_2_6
  • OS and Libraries
    • Connected_Periphs -> RS232_Uart_1 and xps_intc_1
    • Memory Size -> 0x04000000


Modifying UCF File

To make things clearer with the UARTs. Change the following:

  1. fpga_0_RS232_Uart_1 -> fpga_0_RS232_Uart_0
  • 6 Changes
  1. fpga_0_RS232_Uart_2 -> fpga_0_RS232_Uart_1
  • 4 Changes

Modifying MHS File

There are some settings to need to be modified within the MHS File before Synthesizing.

  1. RS232:
  • PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
  • PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
  • PORT fpga_0_RS232_Uart_2_RX_pin = fpga_0_RS232_Uart_2_RX, DIR = I
  • PORT fpga_0_RS232_Uart_2_TX_pin = fpga_0_RS232_Uart_2_TX, DIR = O
  1. to:
  • PORT fpga_0_RS232_Uart_0_RX_pin = fpga_0_RS232_Uart_0_RX, DIR = I
  • PORT fpga_0_RS232_Uart_0_TX_pin = fpga_0_RS232_Uart_0_TX, DIR = O
  • PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
  • PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
  1. Modify ppc405_0:
  • PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
    • PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ_0
  1. Add the following to ppc405_1:
  • PORT CPMC405CLOCK = proc_clk_s
  • PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ_1
  1. Add to plb_1:
  • PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
  • PORT PLB_Clk = sys_clk_s
  • PORT SYS_Rst = sys_bus_reset
  1. Add to ppc405_1_dplb:
  • PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
  • PORT PLB_Clk = sys_clk_s
  • PORT SYS_Rst = sys_bus_reset
  1. Add to ppc405_1_iplb:
  • PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
  • PORT PLB_Clk = sys_clk_s
  • PORT SYS_Rst = sys_bus_reset
  1. Change RS232_Uart_0:
  • PORT RX = fpga_0_RS232_Uart_1_RX
  • PORT TX = fpga_0_RS232_Uart_1_TX
  • PORT Interrupt = RS232_Uart_1_Interrupt

to

  • PORT RX = fpga_0_RS232_Uart_0_RX
  • PORT TX = fpga_0_RS232_Uart_0_TX
  • PORT Interrupt = RS232_Uart_0_Interrupt
  1. Change RS232_Uart_1:
  • PORT RX = fpga_0_RS232_Uart_2_RX
  • PORT TX = fpga_0_RS232_Uart_2_TX
  • PORT Interrupt = RS232_Uart_2_Interrupt

to

  • PORT RX = fpga_0_RS232_Uart_1_RX
  • PORT TX = fpga_0_RS232_Uart_1_TX
  • PORT Interrupt = RS232_Uart_1_Interrupt
  1. Change xps_intc_0:
  • PORT Irq = EICC405EXTINPUTIRQ
  • PORT Intr = RS232_Uart_1_Interrupt & RS232_Uart_2_Interrupt

to

  • PORT Irq = EICC405EXTINPUTIRQ_0
  • PORT Intr = RS232_Uart_0_Interrupt
  1. Add xps_intc_0:
  • PORT Irq = EICC405EXTINPUTIRQ_1
  • PORT Intr = RS232_Uart_1_Interrupt


Configuring Linux

Generating ACE File

== Booting Linux (on Spirit Cluster)

Retrieved from "http://rcs.uncc.edu/wiki/index.php/Linux_on_both_PPCs"
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