Implement userlogic to FCM interface

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Attention

Notes1: Here a double precision floating point unit is used as an example of user-logic IP core.

Notes2: About how to generate cores using coregen, please refer to the coregen tutorial created by Sid: Media:Notes on COREGEN.pdf.

Specification of FCM interface

• Four 32 bit registers as write registers
  • slv_reg0 slv_reg1 slv_reg2 slv_reg3
  • You can write data into these registers by using instructions like lqfcmx(load quad word) in your software application program
• Two 32 bit registers as read registers
  • slv_reg4 slv_reg5
  • You can read data from these registers by using instructions like stdfcmx(store double word) in your software application program
• fcmuserdata is data signal from this fcm interface to userlogic core (128bit)
  • fcmuserdata <= slv_reg0 & slv_reg1 & slv_reg2 & slv_reg3 (vhdl logic)
  • You can also use slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 separately in signal mapping of user IP core
• userfcmdata is data signal from userlogic core to fcm interface registers (64bit)
  • userfcmdata <= slv_reg4 & slv_reg5 (vhdl logic)
  • You can also use slv_reg4 or slv_reg5 separately in signal mapping of user IP core
• fcmuserready is a signal from fcm interface to userlogic indicating whether the input signal of userlogic core is valid (if signal is '1') or not valid (if signal is '0') (1 bit)
• userfcminputready is a signal from user IP core to fcm interface indicate that user IP core is ready for input('1') or not ready('0')(1 bit)
• userfcmready is a a signal from user IP core to fcm interface indicating whether the result of user IP core is ready('1') or not ready ('0') (1 bit)

   (Important: the userfcmready signal has to be connected or set to '1'(if not connected) otherwise the data store can not be completed)

• clock is the clock signal (1 bit)
• reset is the reset signal (1 bit)

Implementing the Double Precision FPU step by step

• Create a Double Precision FPU using COREGEN
• Copy the floating_point_v4_0.vhd file generated by COREGEN to pcores/Fcm_v1_00_a/hdl/vhdl directory
• Copy the floating_point_v4_0.ngc file generated by COREGEN to pcores/Fcm_v1_00_a/netlist directory
• Create a Fcm_v2_1_0.bbd file in pcores/Fcm_v1_00_a/data directory. Put the following code into Fcm_v2_1_0.bbd file(Name of the netlist file of your user IP core)

 FILES
 floating_point_v4_0.ngc

• Create a Fcm_v2_1_0.pao file in pcores/Fcm_v1_00_a/data directory. Put the following code into Fcm_v2_1_0.pao file(Name of the vhd file of your user IP core)

 lib Fcm_v1_00_a Fcm
 lib Fcm_v1_00_a floating_point_v4_0

• Open your Fcm.vhd file in pcores/Fcm_v1_00_a/hdl/vhdl directory, and open your floating_point_v4_0.vho file generated by COREGEN.
• Copy the following code in floating_point_v4_0.vho file to the USER signal declarations section in Fcm.vhd file.(Between line 99 and line 102)

 component floating_point_v4_0
 port (
 a: IN std_logic_VECTOR(63 downto 0);
 b: IN std_logic_VECTOR(63 downto 0);
 operation_nd: IN std_logic;
 operation_rfd: OUT std_logic;
 clk: IN std_logic;
 sclr: IN std_logic;
 ce: IN std_logic;
 result: OUT std_logic_VECTOR(63 downto 0);
 rdy: OUT std_logic);
 end component;

• Copy the following code in floating_point_v4_0.vho file to the user logic section in Fcm.vhd file.(Between line 483 and line 486)

 your_instance_name : floating_point_v4_0
 port map (
 a => a,
 b => b,
 operation_nd => operation_nd,
 operation_rfd => operation_rfd,
 clk => clk,
 sclr => sclr,
 ce => ce,
 result => result,
 rdy => rdy);

• Map signals to your userlogic core, modify the above code as following shows (About the definitions of singals, please refer to the above Interface Specification section)

  DPFPU : floating_point_v4_0
  port map (
  a => fcmuserdata(0 to 63),
  b => fcmuserdata(64 to 127),
  operation_nd => fcmuserready,
  operation_rfd => userfcminputready,
  clk => clock,
  sclr => reset,
  ce => '1',
  result => userfcmdata(0 to 63),
  rdy => userfcmready);

Synthesize the hardware system and generate bitstream. Now, we have a user Double Precision IP core implemented in FCM interface. But how to ultilze the hardware FPU core in software? Let's continue on to the Utilize IP core on APU in software applications