Creating Hardware Base System

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Contents 1 Getting Started 2 Base System Builder Wizard 3 Connect FCB to APU 4 Enable APU in MHS file

Getting Started

This chapter assumes reader has basic knowledge about creating the hardware base system on Xilinx's FPGA.

It's aimed at creating a base system with FCB and enbale APU.

If the reader just get started with FPGA design, it is recommended to refer to previous detailed tutorial Linux 2.6 on ML-410 for general guidelines of building the hardware base system .

Not all of these components are necessary for all projects (and adding more is possible), but use these as tutorial.

Base System Builder Wizard

1. Using Xilinx 10.1i open XPS and Run the Base System Build Wizard
2. Select Board:
   • Board Vendor: Xilinx
   • Board Name: Virtex-4 ML410 Evaluation Platform
   • Board Revision: RCCluster
3. Select Processor: PowerPC
4. Configure PowerPC Processor: Processor Clock 300 MHz
5. Cache setup:
   • Check Enable
6. Configure IO Interfaces (1 of 6):
   • Check XPS UARTLITE
     • Set Baudrate to 115200
     • Check Use Interrupt
   • Uncheck RS232_UART_2
7. Configure IO Interfaces (2 of 6):
   • Uncheck SPI_EEPROM
   • Uncheck LEDs_8Bit
   • Uncheck LCD_OPTIONAL
8. Configure IO Interfaces (3 of 6):
   • Uncheck PCI_Arbiter_0
   • Uncheck PCI32_Bridge
   • Uncheck SysACE_CompactFlash
   • Uncheck IIC_Bus
9. Configure IO Interfaces (4 of 6):
   • Uncheck Ethernet_MAC
   • Uncheck TriMode_MAC_MII
10. Configure IO Interfaces (5 of 6):
    • Uncheck MGT_wrapper
    • Uncheck DDR2_SDRAM
11. Configure IO Interfaces (6 of 6):
    • Uncheck DDR_SDRAM
12. Cache Setup:
    • Check ICache
    • Check DCache
13. Add Internal Peripherals
    • Change Memory Size of BRAM IF CNTRL to: 64 KB
14. Software Setup
    • Uncheck:
      • Memory Test
      • Peripheral Self Test

Connect FCB to APU

Now we have a very simple basic system, and then:

1. Open Ip Catalog Bus and Bridge, add Fabric Co-processor Bus(FCB) IP core to the system.
2. Click Bus Interfaces and expand ppc405_0, connect MFCB to fcb_v10_0 as the following figure 4 shows.

Enable APU in MHS file

To use APU, you will have to enable it in system.mhs file. In system.mhs, find out where ppc405_virtex4 locates, usually it looks like:

 BEGIN ppc405_virtex4
   PARAMETER INSTANCE = ppc405_0
   PARAMETER HW_VER = 2.01.a
   PARAMETER C_FASTEST_PLB_CLOCK = DPLB0
   PARAMETER C_IDCR_BASEADDR = 0b0100000000
   PARAMETER C_IDCR_HIGHADDR = 0b0111111111
   BUS_INTERFACE IPLB0 = plb
   BUS_INTERFACE DPLB0 = plb
   BUS_INTERFACE JTAGPPC = jtagppc_cntlr_0_0
   BUS_INTERFACE RESETPPC = ppc_reset_bus
   BUS_INTERFACE MFCB = fcb_v10_0
   PORT CPMC405CLOCK = proc_clk_s
   PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
 END

Add one line of code into it:

   PARAMETER C_APU_CONTROL = 0x0001

Now the APU is enabled. Let's continue on to the Connect FCM interface to FCB