Creating Custom NPI Core

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Contents 1 About 2 Getting Started 3 Modifying MPD File 4 Modifying PAO File 5 Modifying Wrapper VHD File 6 Modifying User Logic VHD File

About

• Author: Andy Schmidt
• Date: 07/11/08
• Description:' Describes how to add NPI Interface to an existing HW Core

Getting Started

Create a hardware core (if you don't already have one) that you will add the NPI connection to.

Modifying MPD File

Open the MPD file of our core

The Native Port Interface relies on a XIL_NPI Bus type:

BUS_INTERFACE BUS = XIL_NPI, BUS_STD = XIL_NPI,     BUS_TYPE = INITIATOR

Add the NPI Generics:

PARAMETER C_PI_ADDR_WIDTH     = 32, DT = INTEGER
PARAMETER C_PI_DATA_WIDTH     = 64, DT = INTEGER
PARAMETER C_PI_BE_WIDTH       = 8, DT = INTEGER
PARAMETER C_PI_RDWDADDR_WIDTH = 4, DT = INTEGER

Add The NPI Ports (which are on the XIL_NPI Bus):

PORT NPI_Addr              = "Addr",              DIR = O, BUS = XIL_NPI, VEC = [(C_PI_ADDR_WIDTH-1):0], ENDIAN = LITTLE
PORT NPI_AddrReq           = "AddrReq",           DIR = O, BUS = XIL_NPI
PORT NPI_AddrAck           = "AddrAck",           DIR = I, BUS = XIL_NPI
PORT NPI_RNW               = "RNW",               DIR = O, BUS = XIL_NPI
PORT NPI_Size              = "Size",              DIR = O, BUS = XIL_NPI, VEC = [3:0], ENDIAN = LITTLE
PORT NPI_WrFIFO_Data       = "WrFIFO_Data",       DIR = O, BUS = XIL_NPI, VEC = [(C_PI_DATA_WIDTH-1):0], ENDIAN = LITTLE
PORT NPI_WrFIFO_BE         = "WrFIFO_BE",         DIR = O, BUS = XIL_NPI, VEC = [(C_PI_BE_WIDTH-1):0], ENDIAN = LITTLE
PORT NPI_WrFIFO_Push       = "WrFIFO_Push",       DIR = O, BUS = XIL_NPI
PORT NPI_RdFIFO_Data       = "RdFIFO_Data",       DIR = I, BUS = XIL_NPI, VEC = [(C_PI_DATA_WIDTH-1):0], ENDIAN = LITTLE
PORT NPI_RdFIFO_Pop        = "RdFIFO_Pop",        DIR = O, BUS = XIL_NPI
PORT NPI_RdFIFO_RdWdAddr   = "RdFIFO_RdWdAddr",   DIR = I, BUS = XIL_NPI, VEC = [(C_PI_RDWDADDR_WIDTH-1):0], ENDIAN = LITTLE
PORT NPI_WrFIFO_AlmostFull = "WrFIFO_AlmostFull", DIR = I, BUS = XIL_NPI
PORT NPI_WrFIFO_Flush      = "WrFIFO_Flush",      DIR = O, BUS = XIL_NPI
PORT NPI_WrFIFO_Empty      = "WrFIFO_Empty",      DIR = I, BUS = XIL_NPI
PORT NPI_RdFIFO_Empty      = "RdFIFO_Empty",      DIR = I, BUS = XIL_NPI 
PORT NPI_RdFIFO_Flush      = "RdFIFO_Flush",      DIR = O, BUS = XIL_NPI
PORT NPI_RdModWr           = "RdModWr",           DIR = O, BUS = XIL_NPI
PORT NPI_InitDone          = "InitDone",          DIR = I, BUS = XIL_NPI
PORT NPI_RdFIFO_Latency    = "RdFIFO_Latency",    DIR = I, BUS = XIL_NPI, VEC = [1:0], ENDIAN = LITTLE

Add the 200 MHz MPMC Clock Signal:

PORT MPMC_Clk     = "MPMC_Clk",     DIR = I

Modifying PAO File

Since we will be adding a custom component called: npi we need to add it to the Peripheral Analysis Order File (PAO).

Add:

lib <core name> npi vhdl

Modifying Wrapper VHD File

Modifying User Logic VHD File