ChipScope 10.1

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Contents 1 About 2 Getting Started 2.1 Integrated Controller (ICON) 2.2 Integrated Logic Analyzer (ILA) 3 CoreGen's ChipScope Generated Files 4 Connecting the ILA in User Logic VDHL 5 Connecting the ICON in the User Logic VHDL 6 Integrating the Netlist into IP Core 7 Running ChipScope Pro Analyzer

About

• Author: Andy Schmidt
• Last Modified: 07/14/2008
• Notes: This tutorial is aimed at using ChipScope 10.1. This tutorial does NOT cover earlier versions

Getting Started

Launch CoreGen: coregen

We will be using the ML410:

1. File -> New Project
2. Save File somewhere you will remember in case you want to modify or add to this project
3. Specify the following for the Part:
   • Family = Virtex4
   • Device = xc4vfx60
   • Package = ff1152
   • Speed Grade = -11
4. Click OK Button

From the Functions Choose Debug & Verification' and the expand ChipScope Pro. Then follow the next two subsections for ICON and ILA.

Integrated Controller (ICON)

1. Double Click on ICON (ChipScope Pro - Integrated Controller)
2. Name the Component something simple like "icon"
3. Set the Number of Control Ports (Number of ILAs this ICON will control)
4. Click Finish and wait for it to generate the ICON Core

(If you haven't already created the ILA, create the ILA)

Integrated Logic Analyzer (ILA)

1. Double Click on ILA (ChipScope Pro - Integrated Logic Analyzer)
2. Name the Component something simple like "ila"
3. Set the Number of Trigger Ports (Number of Registers / Signals the ILA will sample)
4. Click Next
5. For each Trigger:
   • Set the Port Width (The number of bits in the register)
6. Click Finish and wait for it to generate the ICON Core

CoreGen's ChipScope Generated Files

• .ngc = Netlist file (you will get one for the ICON and one for each ILA you generate )
• .vho = An example template file which you will use to instantiate the component in your User Logic file.
• .cdc = ChipScope ILA Description File, imported into Analzyer.sh later to setup Trigger and Data Ports

Connecting the ILA in User Logic VDHL

1. Change to the directory where you saved your ILA files
2. Open the file: ila.vho
   • <project> is whatever you saved the ILA's NGC name
3. Copy the ILA Core Component Declaration to your user_logic.vhd
   • Put the Declaration before the Begin of your Architecture in your user_logic.vhd
4. Copy the ILA Core Instance to your user_logic.vhd
   • Put the Instance after the Begin of your Architecture in your user_logic.vhd
   • Commonly we put the Instance just before the End of the Architecture of user_logic.vhd
5. Rename the Instance Port Map signals to:
   • => control, to => control0,
   • => clk, to => Bus2IP_Clk,
   • Rename the rest of the trigers to the appropriate signals

Connecting the ICON in the User Logic VHDL

1. Open the file: icon.vho
   • <project> is whatever you saved the ICON's NGC name
2. Copy the ICON Core Component Declaration to your user_logic.vhd
   • Commonly we put the Instance just before the ILA Declaration
3. Copy the ICON Core Singal Declarations to your user_logic.vhd
   • The control0 signal is used by ChipScope
4. Copy the ICON Core Instance to your user_logic.vhd
   • Commonly we put the Instance just before the ILA Instance

Integrating the Netlist into IP Core

In order to use the ILA and ICON created above you would need to either copy the *.ngc files to the implementation directory everytime you wish to synthesize, or a much safer method is to do the following. This will eliminate the chance of forgetting to copy the files over and synthesizing (wasting your time).

• Change to your IP Core's directory
• Create a directory called: netlist at the same level as data, devl, hdl
• Copy the *.edn files from your ChipScope directory to the netlist directory
• Create a file in the data directory called: <core_name_version>.bbd
  • There are already 2 files in the data directory: .pao and .mpd
  • BBD = Black Blox Description
• Add the following Lines to your .bbd file:

FILES
<ILA>.ngc, <ICON>.ngc

• Add the following Line to your .mpd file:

OPTION STYLE = MIX

Running ChipScope Pro Analyzer

After synthesizing the design you will need to open the ChipScope Analyzer Tool. You will connect to the FPGA via the JTAG and download the download.bit all though this tool. (NOTE: For systems with programs that do not fit within BRAM (ex. Linux) you will need to do this step differently.

1. Setup the Computer to use a JTAG connection
   • source /opt/xilinx/jtag.sh
2. Setup Xilinx Tools
   • source /opt/xilinx/10.1i/settings.sh
3. Open Analyzer Tool:
   • analyzer.sh
4. Connect to the FPGA
   • Click the button under the File Menu that looks like 4 boxes called: Open Cable/Search JTAG
   • This will open a box where 2 devices are found, the System_ACE_CF and the XC4VFX60 (our FPGA). Click OK
   • NOTE: After you create and save the project, I suggest opening the project first before connecting, it just makes things easier in the future!
5. Configure the FPGA with your download.bit
   • From the Device Menu choose My_Device 1 (XC4VFX60) and click Configure
6. Select the download.bit of your project
7. Wait for the system to download and program the FGPA
   • NOTE: Look at the status bar at the lower right hand to see the status of the programming
8. After configuring the FPGA you should now see under DEV: 1 MyDevice1 (XC4FX60) your ILA
9. Setup the ILA with your Trigger Points
   • File -> Import -> Select New File and select the ila.cdc file
   • Repeat if you have more than 1 ILA
10. Rename the Trigger Ports
11. Setup Trigger Condition (Event)
12. Re-Download download.bit
13. Set Trigger (F5)
14. View ChipScope Output