FERPS
From RCSWiki
Overview
The Full/Empty Register Pipe or FERP is an implemtation of a FIFO
with control and status signals that provide additional functionality and
control over data being passed between computational components, also known
as active components.
The signals of the FERP are:
- FF: The full flag is active high when the FERP's registers are full
- write: When valid data is available on the input data line, set the write flag to 1 to write data into the FERP, otherwise write should be 0
- d: The data line is used to pass data and its width is specified by the user
- n: These lines allow vector data of dimension n to be passed to the FERP and is used to tell where each vector ends
- excp: The exception line is set if an error (such as divide by 0) occurs and the exception is passed along with the data back to the program to inform it that an error has occurred (and the result is likely incorrect)
- EF: The empty flag is active high when the FERP's registers are *not* empty
- read: When valid data is available on the output data line, read the data then set the read flag to 1 to let the FERP know that the data is no longer valid Otherwise set read to 0
- rst: Resets the FERP to its initial state
Differences in VHDL and JHDL FERP
As shown in the figure below, the VHDL FERP has register space for only one
data "token" while the JHDL version has two sets of registers available to
store data. This difference means that with the JHDL FERP, the full and empty
flag will not change simultaneously. Otherwise, the two implementations of the
FERP are identical.
Special types of FERPs
Since FERPs act like FIFOs to pass data from one component to another,
specialized FERPs have been created to split data from one source to
two sinks (computational components) and to merge data from two
sources to one sink, also called a conform. Figure below shows
how these components are implemented into a dataflow design.
Implementation in a Design
One of the motivations behind creating a custom FIFO like the FERP is the
need for easy and rapid assembly in a variety of designs. The use of the FERP
allows for simple connections to computational components as shown in the JHDL
implementation of a 32 bit adder in Figure 3. Data is passed
from the input FERP to the adder (and from the adder to the output FERP) using
a simplified state machine which checks to make sure the output FERP is not full
and the input FERP is not empty.
To use the JHDL adder, data is first put on the data input line.
Then the valid data is written into the FERP by setting the write flag to one. Notice that the empty flag is also set to one indicating that there is valid data in the input FERP.
Next, the and gate that serves as this design's state machine checks to see if the input FERP has data and if the output FERP is not full. Since these conditions are satisfied the and gate allows data to be read from the input FERP and written to the output FERP. It is important to realize that the adder does not have to implement any of the functions of the state
machine - for this reason, the adder can be easily replaced with a variety of 2 input parts (a multiplier, divider, etc.). Also in this figure the empty flag for the output flag is set to one indicating the valid result has been written into the FERP.
After one more cycle, the output FERP is full which means that the state machine goes back to a waiting state (no reads and writes from the input FERP to the output FERP). Valid data is on the output FERP's data line and will remain there until it is read.
After data is read from the output FERP the read flag is set to say that piece of data is no longer needed. The output data is then invalid and is discarded.
Finally, after all data is read from the output FERP (which has two pieces of data in the JHDL case), the empty and full flags are both zero.
