Custom Cores

From RCSWiki

UPDATE ANDY!

• This section assumes that you have already created a base system as shown in the first step.
• Click on the 'Tools' tab and then click on 'Create/Import Peripheral Wizard' . A window should pop up
  
  
  
  
  
• Click 'Next'
  
  
  
• Since you want to make a new periheral, select the 'Create templates flow'
  
  
  Image:Screenshot17.png
  
  
• Now click on 'To an XPS project' for now, but may be if you get more experienced then you can start building repositories of cores.
  
  
  Image:Screenshot18.png
  
  
• Give a nice name to the core that you are gonna build
  
  
  Image:Screenshot19.png
  
  
• Select the bus that you wanna have your core hooked up to.
  
  
  Image:Screenshot20.png
  
  
• Now select the IPIF Services that you want to use
• If your core needs to be a master on the bus then select 'User Logic Master Support'
• Also, if you need software registers for testing user logic signals (such as a start signal or read count signal), select 'User Logic S/W Register Support'.
• There are many services that you can use, but you may want to read the documentation for each one first
  
  
  Image:Screenshot21.png
  
  
• Next select the number of software registers you need (number of custom signals you want to track) and their respective sizes (32 byte usually).
• Just check Bus2IP_Addr - other signals should be fine using the default signals selected
  
  
  Image:Screenshot22.png
  
  
• Make sure that you click on 'Generate BFM simulation platform for Modelsim '
  
  
  Image:Screenshot23.png
  
  
• Click Next
  
  
  Image:Screenshot24.png
  
  
• Click 'Finish'
  
  
  
• After clicking finish, it is gonna take some time because it is gonna generate a whole bunch of files in the background and EDK may crash.
  
  
  
• In case EDK crashes then just reopen it again
  
  
  Image:Screenshot25.png
  
  
• Now we need to add some cores including the new core that we created to the whole Base System.
  
  
  
• Now click on the 'Project' tab and then click on 'Add/Edit Cores'
  
  
  Image:Screenshot26.png
  
  
• Make sure that you add the following cores apart from the cores that you created. These cores are essential for the Bus Functional Model for Simulation
  
  
  
  • bfm_synch
  • opb_device_bfm
  • opb_monitor_bfm
  • your own core
• In case you chose to add your core to the PLB bus when you created it, add the following cores also since they are needed to simulate the PLB core using the Bus Fucntional Model
  • plb_master_bfm
  • plb_monitor_bfm
  • plb_slave_bfm

  Image:Screenshot27.png
  
  

  
  

• Now click on the 'Bus Connections' tab
  
  
  
• Here you connect the various cores to the busses avaiable.
  
  
  
• Since this is a simple system, this stage shouldnt be a problem at all.
  
  
  Image:Screenshot28.png
  
  
• Now click the 'Addresses' tab and then click on 'Generate addresses'
  
  
  
• Now click on 'Apply' and then 'OK'
  
  
  Image:Screenshot29.png
  
  
• Before generating simulation files, you want to make sure your VHDL code is copied to the user_logic.vhd file so that your VHDL is included in the simulation
• Now go to the 'Tools' tab and then click on 'Generate Simulation Files'
  
  
  
• A small window is gonna popup and click 'OK'
  
  
  Image:Screenshot30.png
  
  
• Set the EDK Library path to '/projects/rtrjvm/modelsim/edk_libs'
  
  
  
• Set the ISE Library path to '/projects/rtrjvm/modelsim/ise_libs'
  
  
  
• Click 'OK'
  
  
  

Image:Screenshot31.png

After the simulation files are created, you can go to the next step which is modelling your core with Modelsim.