Creating Hardware Base System With OPB2PCI Bridge

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Contents

Getting Started

This chapter assumes reader has basic knowledge about creating the hardware base system on Xilinx's FPGA.

It's aimed at creating a base system with OPB2PCI bridge.

If the reader just get started with FPGA design, it is recommended to refer to previous detailed tutorial Linux 2.6 on ML-410for general guidelines of building the hardware base system .

Not all of these components are necessary for all projects (and adding more is possible), but use these to get started.

Base System Builder Wizard

  1. Using Xilinx 8.2i open XPS and Run the Base System Build Wizard
  2. Select Board:
    • Board Vendor: Xilinx
    • Board Name: Virtex-4 ML410 Evaluation Platform
    • Board Revision: B
  3. Select Processor: PowerPC
  4. Configure PowerPC Processor: Processor Clock 300 MHz
  5. Configure IO Interfaces (1 of 5):
    • Check RS232_UART_1
      • Check OPB UART16550
      • Check Use Interrupt
    • Uncheck RS232_UART_2
  6. Configure IO Interfaces (2 of 5):
    • Check DDR_SDRAM_32Mx64
      • Check Use Interrupt
    • Uncheck SPI EEPROM
    • Uncheck LEDs_8Bit
    • Uncheck LCD_OPTIONAL
  7. Configure IO Interfaces (3 of 5):
    • Check PCI_Arbiter_0
    • Check PCI32_Bridge
      • Check Use DMA
      • Check Use Interrupt
    • Check SysACE_CompactFlash
      • Check Use Interrupt
    • Check IIC_Bus
      • Check Use Interrupt
    • Uncheck Ethernet_MAC
  8. Configure IO Interfaces (4 of 5):
    • Check TriMode_MAC_MII
      • Check No DMA
      • Check Use Interrupt
  9. Configure IO Interfaces (5 of 5):
    • Check DDR2_SDRAM_32Mx64
    • Check User Interrupt
  10. Add Internal Peripherals
    • Change Memory Size of BRAM IF CNTRL to: 64 KB
    • Uncheck:
      • Memory Test
      • Peripheral Self Test

OPB2PCI core setting

Open up PCI32_BRIDGE in system assembly view, make sure that

  • IPIF BAR0 Memory Designator is check
  • IPIF BAR1 Memory Designator is uncheck

screen shot for PCI32_BRIDGE

  • PCI address bit that PCI core IDSEL is connected to is set to 16

screen shot for PCI32_BRIDGE

Xilinx Interrupt controller setting

Because Ali15x3 South Bridge can not use IRQ 0 (otherwise Linux will display bad irq 0 later), we have to manually change IRQ assignment in system.mhs. In system.mhs, find out where interrupt controller locates, usually it looks like: 

 BEGIN opb_intc
  PARAMETER INSTANCE = opb_intc_0
  PARAMETER HW_VER = 1.00.c
  PARAMETER C_BASEADDR = 0x41200000
  PARAMETER C_HIGHADDR = 0x4120ffff
  BUS_INTERFACE SOPB = opb
  PORT Irq = EICC405EXTINPUTIRQ
  PORT Intr = RS232_Uart_1_IP2INTC_Irpt & DDR_SDRAM_32Mx64_IP2INTC_Irpt & PCI32_BRIDGE_IP2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & TriMode_MAC_GMII_IP2INTC_Irpt &   
  DDR2_SDRAM_32Mx64_IP2INTC_Irpt & IIC_Bus_IP2INTC_Irpt& fpga_0_PCI32_BRIDGE_PCI_INTA & fpga_0_PCI32_BRIDGE_PCI_INTB & fpga_0_PCI32_BRIDGE_PCI_INTC & fpga_0_PCI32_BRIDGE_PCI_INTD & 
  fpga_0_PCI32_BRIDGE_PCI_SBR_INT
 END

You may move any INTC other than PCI device INT to the end so ALi 15x3 South Bridge will get an IRQ 1. 

  PORT Intr = RS232_Uart_1_IP2INTC_Irpt & DDR_SDRAM_32Mx64_IP2INTC_Irpt & PCI32_BRIDGE_IP2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & TriMode_MAC_GMII_IP2INTC_Irpt &   
  DDR2_SDRAM_32Mx64_IP2INTC_Irpt & fpga_0_PCI32_BRIDGE_PCI_INTA & fpga_0_PCI32_BRIDGE_PCI_INTB & fpga_0_PCI32_BRIDGE_PCI_INTC & fpga_0_PCI32_BRIDGE_PCI_INTD & 
  fpga_0_PCI32_BRIDGE_PCI_SBR_INT & IIC_Bus_IP2INTC_Irpt


Software Platform Settings

After generating the Hardware Base System you need to configure the Software Platform to change the project from a Standalone C project to a Linux 2.6 project. This requires a few steps that need to be done before building and configuring the Linux Kernel. If you miss this step and build the Linux System it will potentially not include all of the hardware you have selected in the BSB Wizard.

  1. From the Software Menu click Software Platform Settings
  2. Under Software Platforms:
    • Under OS & Library Settings (Far Left Side of Dialog Box):
      • Change the OS from Standalone to linux_2_6
  3. Under OS and Libraries (Far Left Side of Dialog Box):
    • Click Connected Periphs and Edit Current Value:
      • Click Add All and then Click OK
    • Set Memory Size to: 0x10000000
    • Set Uart16550 bus clock freq to 100000000
    • Set rootfs type to ramdisk
  4. From the Software Menu click Generate Libraries and BSPs

Tying Hardware Base System and Linux Kernel Together

Copy the xparameters_ml40x.h file from the hardware base system into the Linux PowerPC 405 directory which will be created later. The file is located at: <build directory>/ppc405_0/libsrc/linux_2_6_v1_00_c/linux/arch/ppc/platform/4xx/xparameters/xparameters_ml40x.h

Make sure XPAR_OPB_INTC_0_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_SBR_INT_INTR is not set to 0

The xparameters_ml40x.h file is generated when you Generate Libraries and BSP and consists of the relevant hardware addresses and parameters that Linux will use during its build. The ML40X part refers to Xilinx's ML-403 / 405 boards which the ML410 is very similar too. As of this posting, Xilinx does not directly export the ML-410 xparameters file. There are no changes that need to be made in order to use the file except to copy it to the correct location:

  1. Copy:
    • <build directory>/ppc405_0/libsrc/linux_2_6_v1_00_c/linux/arch/ppc/platform/4xx/xparameters/xparameters_ml40x.h to
    • <linux_directory>/arch/ppc/platform/4xx/xparameters/xparameters_ml300.h (This directory will be created in next chapter)
      • Notice the file is renamed from ml40x to ml300 which you will notice is the Board Version used during Linux Compilation's ml403_defconfig command.


Once the file has been copied, continue on with the Downloading and Configuring PCI & Super I/O for Linux 2.6

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