Creating Hardware Base System For PR
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Contents |
Run BSB Wizard
- 300 MHz Processor
- 115200 UART Lite (Check Interrupt)
- DDR
- No: SPI, LED, LCD, PCI
- SysAce (Check Interrupt)
- IIC (Check Interrupt)
- No: Ethernet_MAC
- Trimode_MAC_MII (Check Interrupt)
- No: DDR2
- Keep MGTs!
- 64 KB BRAM
Pcores Directory
Copy pcores directory from /build/willk/rtr/linux_nopci_jtag/edk/pcores to hardware directory
XPS
- Add The Following Cores from the IP Catalog:
- opb_socket_bridge_left
- opb_socket_bridge_right
- opb_prr
- opb_prr
- DCR Bus
- HW ICAP
- Connect Added Components:
- ppc405_0: MDCR
- opb_socket_bridge_left_0: SOPB
- opb_socket_bridge_left_0: SDCR
- opb_socket_bridge_right_0: SOPB
- opb_socket_bridge_right_0: SDCR
- opb_hwicap_0: SOPB
- Address Assignment:
- opb_socket_bridge_left_0 (on DCR): 64 Bytes
- opb_socket_bridge_right_0 (on DCR): 64 Bytes
- opb_socket_bridge_left_0 (on OPB): 64 KBytes
- opb_socket_bridge_right_0 (on OPB): 64 KBytes
- opb_hwicap_0 (on OPB): 64 KBytes
- Click "Generate Addresses" Button
MHS Settings
- Move the following components above ppc405_0 (to adjust synthesis order):
- opb_prr_0
- opb_prr_1
- socket bridge left
- socket bridge right
- hwicap
- Following Will's MHS File add the following Ports:
To socket_bridge_right:
PORT ROPB_Rst = ROPB_Rst_0 PORT ROPB_ABus = ROPB_ABus_0 PORT ROPB_BE = ROPB_BE_0 PORT ROPB_RNW = ROPB_RNW_0 PORT ROPB_select = ROPB_select_0 PORT ROPB_seqAddr = ROPB_seqAddr_0 PORT ROPB_DBus = ROPB_DBus_0 PORT RSln_DBus = RSl_DBus_0 PORT RSln_errAck = RSl_errAck_0 PORT RSln_retry = RSl_retry_0 PORT RSln_toutSup = RSl_toutSup_0 PORT RSln_xferAck = RSl_xferAck_0 PORT ROPB_Clk = ROPB_Clk_0
To socket_bridge_left:
PORT ROPB_Clk = ROPB_Clk_1 PORT ROPB_Rst = ROPB_Rst_1 PORT ROPB_ABus = ROPB_ABus_1 PORT ROPB_BE = ROPB_BE_1 PORT ROPB_RNW = ROPB_RNW_1 PORT ROPB_select = ROPB_select_1 PORT ROPB_seqAddr = ROPB_seqAddr_1 PORT ROPB_DBus = ROPB_DBus_1 PORT RSln_DBus = RSl_DBus_1 PORT RSln_errAck = RSl_errAck_1 PORT RSln_retry = RSl_retry_1 PORT RSln_toutSup = RSl_toutSup_1 PORT RSln_xferAck = RSl_xferAck_1
To opb_prr_0:
PORT OPB_Clk = ROPB_Clk_0 PORT OPB_Rst = ROPB_Rst_0 PORT OPB_ABus = ROPB_ABus_0 PORT OPB_BE = ROPB_BE_0 PORT OPB_RNW = ROPB_RNW_0 PORT OPB_select = ROPB_select_0 PORT OPB_seqAddr = ROPB_seqAddr_0 PORT OPB_DBus = ROPB_DBus_0 PORT Sl_DBus = RSl_DBus_0 PORT Sl_errAck = RSl_errAck_0 PORT Sl_retry = RSl_retry_0 PORT Sl_toutSup = RSl_toutSup_0 PORT Sl_xferAck = RSl_xferAck_0
To opb_prr_1:
PORT OPB_Clk = ROPB_Clk_1 PORT OPB_Rst = ROPB_Rst_1 PORT OPB_ABus = ROPB_ABus_1 PORT OPB_BE = ROPB_BE_1 PORT OPB_RNW = ROPB_RNW_1 PORT OPB_select = ROPB_select_1 PORT OPB_seqAddr = ROPB_seqAddr_1 PORT OPB_DBus = ROPB_DBus_1 PORT Sl_DBus = RSl_DBus_1 PORT Sl_errAck = RSl_errAck_1 PORT Sl_retry = RSl_retry_1 PORT Sl_toutSup = RSl_toutSup_1 PORT Sl_xferAck = RSl_xferAck_1
To ppc405_0:
PORT CPMDCRCLK = sys_clk_s
To opb_hwicap_0 change:
PARAMETER HW_VER = 1.10.a to 1.00.b
Software Platform Settings
- OS: linux_2_6
- Connected Peripheral: RS232, SysAce, IIC, TEMAC, Intc
- Memory Size: 0x04000000
- UART Freq: 100000000
Build Libraries and Netlist
- Generate Libraries and BSPs
- Generate Netlist
- Don't Generate Bitstream (we will do that with PlanAhead)
Modifying xparameters_ml403.h
Either before or after you copy the xparameters_ml403.h" file you will need add the following to the end of the file.
#define XPAR_HWICAP_0_BASEADDR XPAR_OPB_HWICAP_0_BASEADDR #define XPAR_HWICAP_0_HIGHADDR XPAR_OPB_HWICAP_0_HIGHADDR #define XPAR_HWICAP_0_DEVICE_ID XPAR_OPB_HWICAP_0_DEVICE_ID
The Reason for adding this is because 9.1 has the HWICAP connected to the OPB whereas newer versions of XPS has it connected to the PLB.
It is important that you do this before you compile Linux, otherwise when you boot Linux, you will notice the HWICAP is not registered!
Next, follow the Using PlanAhead With Partial Reconfiguration on the ML-410 Tutorial
