Connect FERPs

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1 Using the 16 Input Output BRAM - FERP VHDL/JHDL templates
2 Introduction
3 Address Decoding
4 Address Decoding with an Example
5 Address Decoding With Diagrams

Using the 16 Input Output BRAM - FERP VHDL/JHDL templates

Important Note : before you start reading the page, make sure that you have a design ready in hand which is connected to FERP's. If you want to know about FERP's click here

Introduction

This file gives you a brief idea of the addressing structure that has been implemented for doing High Performance Applications as a slave peripheral IP Core on the ML-310 Board which hosts a Xilinx Virtex II - Pro FPGA with a lot of other capabilites.

Address Decoding

The OPB bus to which the following core is attached to has a 32 bit Address bus.

Bits 0-14
- Not Used
Bit 15
- Select whether Input Or Output
- -- Input
- -- Output
Bits 16-19
- Select which Input / Output Fifo-Ferp to use
Bit 20
- Bit that determines whether count registers or BRAM is being addressed
- 0 - Address BRAM
  - Bits 21 - 29
    - Bits to address the BRAM
- 1 - Address regsiters
  - Bits 28 - 29
    - 01 - Read Count
    - 10 - Write Count
Bits 30 - 31
- Not Used

Address Decoding with an Example

Assume that you are using Input FIFO - FERP 10 and Output FIFO - FERP 20 with a base address of 0x93000000. Always keep in mind that a number between 0 - 15 represents an Input FIFO - FERP and number between 16 - 31 represents an Output FIFO - FERP.

Input FIFO-FERP

Writing a Write Count to the Input FIFO - FERP 10
- Base Address : 0x93000000
- FIFO - FERP 10 : Bits 15 - 19 (01010) t 0x0000A000
- BRAM/Register : Bit 20 (1) 0x00000800
- Write Count : Bits 28 - 29 (01) 0x00000004
- Complete Address 0x9300A804
Writing a value to the first entry in the BRAM in Input FIFO - FERP 10
- Base Address : 0x93000000
- FIFO - FERP 10 : Bits 15 - 19 (01010) 0x0000A000
- BRAM/Register : Bit 20 (0) 0x00000000
- Bram Address : Bits 21 - 29 (000000000) 0x00000000
- Complete Address 0x9300A000
Writing a value to the second entry in the BRAM in Input FIFO - FERP 10
- Base Address : 0x93000000
- FIFO - FERP 10 : Bits 15 - 19 (01010) 0x0000A000
- BRAM/Register : Bit 20 (0) 0x00000000
- Bram Address : Bits 21 - 29 (000000001) 0x00000004
- Complete Address 0x9300A004
Reading value from the Read Count in Input FIFO - FERP 10
- Base Address : 0x93000000
- FIFO - FERP 10 : Bits 15 - 19 (01010) 0x0000A000
- BRAM/Register : Bit 20 (1) 0x00000800
- Write Count : Bits 28 - 29 (10) 0x00000008
- Complete Address 0x9300A808

Output FIFO-FERP

Reading value from the WriteCount in Output FIFO - FERP 20
- Base Address : 0x93000000
- FIFO - FERP 20 : Bits 15 - 19 (11010) 0x0001A000
- BRAM/Register : Bit 20 (1) 0x00000800
- Write Count : Bits 28 - 29 (01) 0x00000004
- Complete Address 0x9301A804
Reading the first entry from the BRAM of the Output FIFO - FERP 11
- Base Address : 0x93000000
- FIFO - FERP 20 : Bits 15 - 19 (11010) 0x0001A000
- BRAM/Register : Bit 20 (0) 0x00000000
- Bram Address : Bits 21 - 29 (000000000) 0x00000000
- Complete Address 0x9301A000
Reading the second entry from the BRAM of the Output FIFO - FERP 11
- Base Address : 0x93000000
- FIFO - FERP 20 : Bits 15 - 19 (11010) 0x0001A000
- BRAM/Register : Bit 20 (1) 0x00000000
- Write Count : Bits 21 - 29 (000000001) 0x00000004
- Complete Address 0x9301A004