Add user constraints for RGMII

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1 Getting Started
2 Base System Builder
3 Modifying system.ucf
4 Modifying system.mhs

Getting Started

The base system originally generated by Xilinx Base System Builder Wizard comes with LLTEMAC as well as MII interface. It works pretty well under 100Mbps with Fast Ethernet. The on-board physical layer (PHY) - Marvell chip 88E1111 - can be configured to use either MII or RGMII. To make LLTEMAC RGMII work on ML-410, changes have to be made on both hardware and Linux configuration.
For hardware, we need to change the interface between LLTEMAC and Marvell 88E1111 from MII to RGMII through user constraints file.

Base System Builder

When being asked to configure LLTEMAC core, check Scatter gather DMA option and Interrupt.

Modifying system.ucf

The original MII interface is defined in system.ucf as following:

 Net fpga_0_TriMode_MAC_MII_MII_TXD_0_pin<3> LOC = K9;
 Net fpga_0_TriMode_MAC_MII_MII_TXD_0_pin<3> IOSTANDARD=LVCMOS33;
 Net fpga_0_TriMode_MAC_MII_MII_TXD_0_pin<2> LOC = K11;
 Net fpga_0_TriMode_MAC_MII_MII_TXD_0_pin<2> IOSTANDARD=LVCMOS33;
 Net fpga_0_TriMode_MAC_MII_MII_TXD_0_pin<1> LOC = K12;
 Net fpga_0_TriMode_MAC_MII_MII_TXD_0_pin<1> IOSTANDARD=LVCMOS33;
 Net fpga_0_TriMode_MAC_MII_MII_TXD_0_pin<0> LOC = K13;
 Net fpga_0_TriMode_MAC_MII_MII_TXD_0_pin<0> IOSTANDARD=LVCMOS33;
 Net fpga_0_TriMode_MAC_MII_MII_TX_EN_0_pin LOC = L11;
 Net fpga_0_TriMode_MAC_MII_MII_TX_EN_0_pin IOSTANDARD=LVCMOS33;
 Net fpga_0_TriMode_MAC_MII_MII_TX_ER_0_pin LOC = L14;
 Net fpga_0_TriMode_MAC_MII_MII_TX_ER_0_pin IOSTANDARD=LVCMOS25;
 Net fpga_0_TriMode_MAC_MII_MII_RXD_0_pin<3> LOC = J9;
 Net fpga_0_TriMode_MAC_MII_MII_RXD_0_pin<3> IOSTANDARD=LVCMOS33;
 Net fpga_0_TriMode_MAC_MII_MII_RXD_0_pin<2> LOC = J10;
 Net fpga_0_TriMode_MAC_MII_MII_RXD_0_pin<2> IOSTANDARD=LVCMOS33;
 Net fpga_0_TriMode_MAC_MII_MII_RXD_0_pin<1> LOC = J11;
 Net fpga_0_TriMode_MAC_MII_MII_RXD_0_pin<1> IOSTANDARD=LVCMOS33;
 Net fpga_0_TriMode_MAC_MII_MII_RXD_0_pin<0> LOC = J12;
 Net fpga_0_TriMode_MAC_MII_MII_RXD_0_pin<0> IOSTANDARD=LVCMOS33;
 Net fpga_0_TriMode_MAC_MII_MII_RX_DV_0_pin LOC = H12;
 Net fpga_0_TriMode_MAC_MII_MII_RX_DV_0_pin IOSTANDARD=LVCMOS33;
 Net fpga_0_TriMode_MAC_MII_MII_RX_ER_0_pin LOC = H18;
 Net fpga_0_TriMode_MAC_MII_MII_RX_ER_0_pin IOSTANDARD=LVCMOS25;
 Net fpga_0_TriMode_MAC_MII_MII_TX_CLK_0_pin LOC=J14;
 Net fpga_0_TriMode_MAC_MII_MII_TX_CLK_0_pin IOSTANDARD=LVCMOS25;
 Net fpga_0_TriMode_MAC_MII_MII_RX_CLK_0_pin LOC=K19;
 Net fpga_0_TriMode_MAC_MII_MII_RX_CLK_0_pin IOSTANDARD=LVCMOS25;

Make a change to

 NET RGMII_TXD_0<3> LOC = K9  | IOSTANDARD=LVCMOS33 | SLEW=FAST;
 NET RGMII_TXD_0<2> LOC = K11 | IOSTANDARD=LVCMOS33 | SLEW=FAST;
 NET RGMII_TXD_0<1> LOC = K12 | IOSTANDARD=LVCMOS33 | SLEW=FAST;
 NET RGMII_TXD_0<0> LOC = K13 | IOSTANDARD=LVCMOS33 | SLEW=FAST;
 NET RGMII_TX_CTL_0 LOC = L11 | IOSTANDARD=LVCMOS33 | SLEW=FAST;
 NET RGMII_TXC_0    LOC = J19 | IOSTANDARD=LVCMOS25 | SLEW=FAST;
 NET RGMII_RXD_0<3> LOC = J9  | IOSTANDARD=LVCMOS33; 
 NET RGMII_RXD_0<2> LOC = J10 | IOSTANDARD=LVCMOS33;
 NET RGMII_RXD_0<1> LOC = J11 | IOSTANDARD=LVCMOS33;
 NET RGMII_RXD_0<0> LOC = J12 | IOSTANDARD=LVCMOS33;
 NET RGMII_RX_CTL_0 LOC = H12 | IOSTANDARD=LVCMOS33;
 NET RGMII_RXC_0    LOC = K19 | IOSTANDARD=LVCMOS25;

The original additional TriMode_MAC_MII constraints is defined in system.ucf as following:

 #### Additional TriMode_MAC_MII constraints
 NET "*tx_gmii_mii_clk_in_0_i"    TNM_NET = "clk_phy_tx_clk0";
 TIMESPEC "TS_phy_tx_clk0"            = PERIOD "clk_phy_tx_clk0" 7200 ps HIGH 50 %;
 NET "*tx_client_clk_in_0_i"      TNM_NET = "clk_client_tx_clk0";
 TIMESPEC "TS_client_tx_clk0"            = PERIOD "clk_client_tx_clk0" 7200 ps HIGH 50 %;
 NET "*rx_client_clk_in_0_i"      TNM_NET = "clk_client_rx_clk0";
 TIMESPEC "TS_client_rx_clk0"            = PERIOD "clk_client_rx_clk0" 7200 ps HIGH 50 %;
 NET "*mii_rx_clk_0_i"            TNM_NET = "clk_phy_rx_clk0";
 TIMESPEC "TS_phy_rx_clk0"               = PERIOD "clk_phy_rx_clk0" 7200 ps HIGH 50 %;
 #################### EMAC 0 MII Constraints ########################
 INST "*mii0?RXD_TO_MAC*"    IOB = true;
 INST "*mii0?RX_DV_TO_MAC"   IOB = true;
 INST "*mii0?RX_ER_TO_MAC"   IOB = true;
 INST "fpga_0_TriMode_MAC_MII_MII_TXD_0_pin<?>"     TNM = "sig_mii_tx_0";
 INST "fpga_0_TriMode_MAC_MII_MII_TX_EN_0_pin"      TNM = "sig_mii_tx_0";
 INST "fpga_0_TriMode_MAC_MII_MII_TX_ER_0_pin"      TNM = "sig_mii_tx_0";
 INST "fpga_0_TriMode_MAC_MII_MII_RXD_0_pin<?>"     TNM = "sig_mii_rx_0";
 INST "fpga_0_TriMode_MAC_MII_MII_RX_DV_0_pin"      TNM = "sig_mii_rx_0";
 INST "fpga_0_TriMode_MAC_MII_MII_RX_ER_0_pin"      TNM = "sig_mii_rx_0";
 # Need to TIG between the LocalLink clock and the rx_client and tx_client clocks
 NET "*/LlinkTemac0_CLK*" TNM_NET = "LLCLK";
 TIMESPEC "TS_LL_CLK_2_RX_CLIENT_CLK"  = FROM LLCLK TO clk_client_rx_clk0 8000 ps DATAPATHONLY;
 TIMESPEC "TS_LL_CLK_2_TX_CLIENT_CLK"  = FROM LLCLK TO clk_client_tx_clk0 8000 ps DATAPATHONLY;
 TIMESPEC "TS_RX_CLIENT_CLK_2_LL_CLK"  = FROM clk_client_rx_clk0 TO LLCLK 10000 ps DATAPATHONLY;
 TIMESPEC "TS_TX_CLIENT_CLK_2_LL_CLK"  = FROM clk_client_tx_clk0 TO LLCLK 10000 ps DATAPATHONLY;

Make a change to

 #### Additional TriMode_MAC_RGMII constraints
 INST "TriMode_MAC_MII/*?v4_emac" LOC = "EMAC_X0Y1";
 #INST "*idelayctrl0" LOC = "IDELAYCTRL_X2Y7";
 NET "*tx_gmii_mii_clk_in_0*" TNM_NET = "clk_phy_tx_clk0";
 NET "*tx_gmii_mii_clk_out_0*" TNM_NET = "clk_phy_tx_clk0";
 TIMESPEC "TS_phy_tx_clk0" = PERIOD "clk_phy_tx_clk0" 7200 ps HIGH 50 %;
 NET "*rgmii_rxc_0*" TNM_NET = "clk_phy_rx_clk0";
 NET "*rgmii_rxc_delay_0*" TNM_NET = "clk_phy_rx_clk0";
 NET "*rgmii_rxc_ibufg*" TNM_NET = "clk_phy_rx_clk0";
 TIMESPEC "TS_phy_rx_clk0" = PERIOD "clk_phy_rx_clk0" 7200 ps HIGH 50 %;
 NET "*tx_client_clk_in_0*" TNM_NET = "clk_client_tx_clk0";
 NET "*tx_client_clk_out_0*" TNM_NET = "clk_client_tx_clk0";
 TIMESPEC "TS_client_tx_clk0" = PERIOD "clk_client_tx_clk0" 7200 ps HIGH 50 %;
 NET "*rx_client_clk_in_0*" TNM_NET = "clk_client_rx_clk0";
 NET "*rx_client_clk_out_0*" TNM_NET = "clk_client_rx_clk0";
 TIMESPEC "TS_client_rx_clk0" = PERIOD "clk_client_rx_clk0" 7200 ps HIGH 50 %;
 # Timing constraints for IDDR/ODDR paths
 INST "*rgmii_rxd?_iddr"         TNM = "rgmii_iddr";
 INST "*rgmii_rx_ctl_iddr"       TNM = "rgmii_iddr";
 INST "*rgmii_txd?_oddr"         TNM = "rgmii_oddr";
 INST "*rgmii_tx_ctl_oddr"       TNM = "rgmii_oddr";
 INST "*v4_emac"                 TNM = "emac";
 NET "*rgmii_rx_ctl_falling_?_i" TPTHRU = "inpath";
 NET "*rgmii_rxd_falling_?_i<?>" TPTHRU = "inpath";
 NET "*rgmii_txd_falling_?_i<?>" TPTHRU = "outpath";
 NET "*rgmii_tx_ctl_falling_?_i" TPTHRU = "outpath";
 NET "*rgmii_tx_ctl_rising_?_i" TPTHRU = "outpath";
 TIMESPEC "TSin"=FROM "rgmii_iddr" THRU "inpath" TO "emac" 7200 ps DATAPATHONLY;
 TIMESPEC "TSout"=FROM "emac" THRU "outpath" TO "rgmii_oddr" 7200 ps DATAPATHONLY;
 # IDELAY on data path to align it with the clock
 INST "*rgmii0/*rgmii_rxd_delay*" IOBDELAY_TYPE = FIXED;
 INST "*rgmii0/*rgmii_rxd_delay*" IOBDELAY_VALUE = 36;
 INST "*rgmii0/*rgmii_rx_ctl_delay*" IOBDELAY_TYPE = FIXED;
 INST "*rgmii0/*rgmii_rx_ctl_delay*" IOBDELAY_VALUE = 36;
 INST "*gmii_rx_clk_0_delay" IOBDELAY_TYPE = FIXED;
 INST "*gmii_rx_clk_0_delay" IOBDELAY_VALUE = 0;
 # RGMII Spec: 1ns setup 1ns hold, DDR
 INST "rgmii_rxd_0<?>"           TNM = "rgmii_rx_0_grp";
 INST "rgmii_rx_ctl_0"           TNM = "rgmii_rx_0_grp";
 #TIMEGRP "rgmii_rx_0_grp" OFFSET = IN -7 ns VALID 2 ns BEFORE "RGMII_RXC_0" LOW;
 TIMEGRP "rgmii_rx_0_grp" OFFSET = IN -1 ns VALID 2 ns BEFORE "RGMII_RXC_0" LOW;
 # Need to TIG between the LocalLink clock and the rx_client and tx_client clocks
 NET "sys_clk_s" TNM_NET = "LLCLK";
 TIMESPEC "TS_LL_CLK_2_RX_CLIENT_CLK"  = FROM LLCLK TO clk_client_rx_clk0 8000 ps DATAPATHONLY;
 TIMESPEC "TS_LL_CLK_2_TX_CLIENT_CLK"  = FROM LLCLK TO clk_client_tx_clk0 8000 ps DATAPATHONLY;
 TIMESPEC "TS_RX_CLIENT_CLK_2_LL_CLK"  = FROM clk_client_rx_clk0 TO LLCLK 8000 ps DATAPATHONLY;
 TIMESPEC "TS_TX_CLIENT_CLK_2_LL_CLK"  = FROM clk_client_tx_clk0 TO LLCLK 8000 ps DATAPATHONLY;

Modifying system.mhs

The original MII interface is defined in system.mhs as following:

 PORT fpga_0_TriMode_MAC_MII_MII_TXD_0_pin = fpga_0_TriMode_MAC_MII_MII_TXD_0, DIR = O, VEC = [3:0]
 PORT fpga_0_TriMode_MAC_MII_MII_TX_EN_0_pin = fpga_0_TriMode_MAC_MII_MII_TX_EN_0, DIR = O
 PORT fpga_0_TriMode_MAC_MII_MII_TX_ER_0_pin = fpga_0_TriMode_MAC_MII_MII_TX_ER_0, DIR = O
 PORT fpga_0_TriMode_MAC_MII_MII_RXD_0_pin = fpga_0_TriMode_MAC_MII_MII_RXD_0, DIR = I, VEC = [3:0]
 PORT fpga_0_TriMode_MAC_MII_MII_RX_DV_0_pin = fpga_0_TriMode_MAC_MII_MII_RX_DV_0, DIR = I
 PORT fpga_0_TriMode_MAC_MII_MII_RX_ER_0_pin = fpga_0_TriMode_MAC_MII_MII_RX_ER_0, DIR = I
 PORT fpga_0_TriMode_MAC_MII_MII_TX_CLK_0_pin = fpga_0_TriMode_MAC_MII_MII_TX_CLK_0, DIR = I
 PORT fpga_0_TriMode_MAC_MII_MII_RX_CLK_0_pin = fpga_0_TriMode_MAC_MII_MII_RX_CLK_0, DIR = I

Make a change to

 PORT RGMII_TXD_0 = RGMII_TXD_0, DIR = O, VEC = [3:0]
 PORT RGMII_TX_CTL_0 = RGMII_TX_CTL_0, DIR = O
 PORT RGMII_TXC_0 = RGMII_TXC_0, DIR = O
 PORT RGMII_RXD_0 = RGMII_RXD_0, DIR = I, VEC = [3:0]
 PORT RGMII_RX_CTL_0 = RGMII_RX_CTL_0, DIR = I
 PORT RGMII_RXC_0 = RGMII_RXC_0, DIR = I

The original interface defined in xps_ll_temac entity is

 BEGIN xps_ll_temac
  PARAMETER INSTANCE = TriMode_MAC_MII
  PARAMETER HW_VER = 1.01.b
  PARAMETER C_SPLB_CLK_PERIOD_PS = 10000
  PARAMETER C_PHY_TYPE = 0
  PARAMETER C_TEMAC_TYPE = 1
  PARAMETER C_BUS2CORE_CLK_RATIO = 1
  PARAMETER C_BASEADDR = 0x81c00000
  PARAMETER C_HIGHADDR = 0x81c0ffff
  BUS_INTERFACE SPLB = plb
  BUS_INTERFACE LLINK0 = TriMode_MAC_MIIllink0
  PORT MII_TXD_0 = fpga_0_TriMode_MAC_MII_MII_TXD_0
  PORT MII_TX_EN_0 = fpga_0_TriMode_MAC_MII_MII_TX_EN_0
  PORT MII_TX_ER_0 = fpga_0_TriMode_MAC_MII_MII_TX_ER_0
  PORT MII_RXD_0 = fpga_0_TriMode_MAC_MII_MII_RXD_0
  PORT MII_RX_DV_0 = fpga_0_TriMode_MAC_MII_MII_RX_DV_0
  PORT MII_RX_ER_0 = fpga_0_TriMode_MAC_MII_MII_RX_ER_0
  PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_MII_MII_TX_CLK_0
  PORT MII_RX_CLK_0 = fpga_0_TriMode_MAC_MII_MII_RX_CLK_0
  PORT MDIO_0 = fpga_0_TriMode_MAC_MII_MDIO_0
  PORT MDC_0 = fpga_0_TriMode_MAC_MII_MDC_0
  PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_MII_TemacPhy_RST_n
  PORT LlinkTemac0_CLK = sys_clk_s
  PORT TemacIntc0_Irpt = TriMode_MAC_MII_TemacIntc0_Irpt
 END

Make a change to

 BEGIN xps_ll_temac
  PARAMETER INSTANCE = TriMode_MAC_MII
  PARAMETER HW_VER = 1.01.b
  PARAMETER C_PHY_TYPE = 2
  PARAMETER C_BUS2CORE_CLK_RATIO = 1
  PARAMETER C_BASEADDR = 0x81c00000
  PARAMETER C_HIGHADDR = 0x81c0ffff
  PARAMETER C_NUM_IDELAYCTRL = 3
  PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X2Y6-IDELAYCTRL_X2Y7-IDELAYCTRL_X1Y5
  BUS_INTERFACE SPLB = plb
  BUS_INTERFACE LLINK0 = TriMode_MAC_MII_LLINK0
  PORT GTX_CLK_0 = GTX_CLK0
  PORT RGMII_TXD_0 = RGMII_TXD_0
  PORT RGMII_TX_CTL_0 = RGMII_TX_CTL_0
  PORT RGMII_TXC_0 = RGMII_TXC_0
  PORT RGMII_RXD_0 = RGMII_RXD_0
  PORT RGMII_RX_CTL_0 = RGMII_RX_CTL_0
  PORT RGMII_RXC_0 = RGMII_RXC_0
  PORT REFCLK = DDR2_SDRAM_mpmc_clk_s
  PORT MDIO_0 = fpga_0_TriMode_MAC_MII_MDIO_0
  PORT MDC_0 = fpga_0_TriMode_MAC_MII_MDC_0
  PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_MII_TemacPhy_RST_n
  PORT LlinkTemac0_CLK = sys_clk_s
  PORT TemacIntc0_Irpt = TriMode_MAC_MII_TemacIntc0_Irpt
 END

In the entity of clock_generator, add

 PARAMETER C_CLKOUT4_FREQ = 125000000
 PARAMETER C_CLKOUT4_BUF = TRUE
 PARAMETER C_CLKOUT4_PHASE = 0
 PARAMETER C_CLKOUT4_GROUP = NONE
 PORT CLKOUT4 = GTX_CLK0

Continue on to the Configuring Linux Device Driver

Retrieved from "http://rcs.uncc.edu/wiki/index.php/Add_user_constraints_for_RGMII"

Add user constraints for RGMII

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Contents

Getting Started

Base System Builder

Modifying system.ucf

Modifying system.mhs

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