AMFS
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Contents |
Ashwin Mendon's Hardware Filesystem
Objective
The goal of this project was to verify the feasibility of implementing a filesystem directly in FPGA hardware. Such an approach has the potential of providing direct, high bandwidth access to data sets for the compute cores on the FPGA. The filesystem is targeted for high-performance computing applications, meaning that it is designed to handle small number of large files.
The Core
To evaluate the feasibility and performance of a hardware filesystem core it was necessary to set up an experimental apparatus. First, a software reference design was created to provide a detailed specification of the filesystem layout and reference for each operation. A HWFS core was then implemented using VHDL targeting a Virtex-4 ML410 platform FPGA. To handle complexity and manage risk, the core was first tested in simlulation using a simple behavioral model of the SATA host controller along with a test bench in Modelsim. The functionality of the fundamental filesystem operations open, read, write, delete and lseek were verified. The performance was checked using file sizes ranging from 1 KB to 5 GB. The filesystem achieves efficient run-time performance, i.e. the overheads have a lesser effect on the latencies for large file (over 100 KB). Synthesis results show that the core uses a modest 3 % of the slices of a Xilinx Virtex-4 FX60 device.
Current Status
The AMFS has been successfully tested on an FPGA with a RAM Disk on off-chip DDR2 memory. Though, SATA host controller cores are available for purchase, the cost is such that we found it practical to first test the core on the FPGA using the Xilinx Multi-Port Memory Controller (MPMC) and a custom Native Port Interface (NPI) for DDR2. The filesystem core is designed with a generic interface. Once, the SATA IP core is purchased, a simple interface can be created between AMFS and SATA controller to port the RAM Disk implementation to a SATA implementation.
Related Publications
Ashwin Mendon and Ron Sass. A Hardware Filesystem Implementation for High-Speed Secondary Storage. Proceedings of the IEEE International Conference on Reconfigurable Computing and FPGAs, Cancun. Dec 2008.
